Building Logic Gate PCBs Using CMOS Technology

I wanted to start my own self-learning journey in integrated circuit (IC) design, so I decided to test the waters a bit in digital IC design. The most fundamental components in digital circuitry are logic gates. Although these gates already exist in IC forms, I wanted to explore how they could be constructed on the transistor level.

For this project, I designed and built the three most fundamental logic gates in Boolean logic: NOT, AND and OR. Each uses Complementary Metal-Oxide-Semiconductor (CMOS) logic with complementary N-channel and P-channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) arranged to perform their respective logic functions.

To make the circuits more user-friendly and compact, I designed them as dual in-line package (DIP)-style printed circuit boards (PCBs) that could be used as individual modules. The circuits were simulated in LTspice before the schematics and PCB layouts were made in KiCad initially, then the final designs in EasyEDA.

After fabrication and assembly, I tested all three boards using signals generated from an Arduino board to confirm that their outputs matched their expected truth tables.

Electronic Components

1. 2N7002 - N-channel MOSFET (SOT-23) - AliExpress link here
2. BSS84 - P-channel MOSFET (SOT-23) - AliExpress link here
3. Custom PCBs for the NOT, AND and OR logic gates
4. 2.54mm pin headers - AliExpress link here
5. Breadboard
6. Jumper wires
7. White LED
8. 220ohm resistor
9. DC power supply - AliExpress link here

Software

1. LTspice - For circuit simulation and waveform analysis
2. EasyEDA/KiCad - Schematic drawings, PCB layout and 3D visualization

Tools and Equipment

1. Soldering iron and solder/Heating plate
2. Tweezers
3. Solder paste
4. Digital multimeter
5. Digital oscilloscope (DSO153) - AliExpress link here
6. Computer for circuit simulation and PCB design
7. Arduino Uno/Mega/Nano with a USB cable

Project Files

1. The schematics, PCB designs and simulation files are in my GitHub repository

Discrete CMOS Logic Gate Arrays

As mentioned before, CMOS stands for Complementary Metal-Oxide-Semiconductor. It's the technology used in modern digital integrated circuits like microprocessors and memory devices.

CMOS circuits use two types of MOSFETs:

1. NMOS (N-channel MOSFET): conducts when the gate to source voltage is greater than its threshold voltage.
2. PMOS (P-channel MOSFET): conducts when the gate to source voltage is less than its threshold voltage.

The transistors form two complementary networks:

1. Pull-Up Network (PUN): The pull-up network uses PMOS transistors connected between the positive voltage supply (VDD) and the output. When the network conducts, it pulls the output toward a logic HIGH state.
2. Pull-Down Network (PDN): The pull-down network uses NMOS transistors connected between the output and ground (GND). When this network conducts, it pulls the output toward a logic LOW.

Constructing the Logic Gates

For the three logic gates built, I used three different configurations.

1. The CMOS inverter used one PMOS and one NMOS

Because of CMOS technology and its uniqueness, the circuits for the AND and OR logic gates are actually NAND and NOR circuits combined with NOT gates. So:

1. The AND gate uses parallel PMOS transistors and series NMOS transistors for the NAND aspect of the circuit and a NOT configuration on the output.
2. The OR uses series PMOS transistors and parallel NMOS transistors for the NOR aspect of the circuit and a NOT configuration on the output.

The first and easiest circuit to design was the NOT Gate (Inverter).

The function of the NOT gate is to invert a given input or produce the opposite to its input. So, if the input is LOW (0), the output is HIGH (1) and vice versa.

Circuit Design

For this circuit, I used:

1. BSS84 (PMOS): forms the pull-up network
2. 2N7002 (NMOS): forms the pull-down network

The source of the PMOS is connected to the positive supply voltage (VDD) while the source of the NMOS transistor is connected to ground (GND).

Both transistor gates are connected together to form the input (A) and their drains form the output (Y).

Operating Principle

1. When the input is LOW (0 V), the NMOS transistor is OFF because its gate-to-source voltage is below the threshold voltage. At the same time, the PMOS transistor is ON because its gate is at 0 V while its source is at VDD, giving a gate-to-source voltage of about -VDD, which is below its threshold. With the PMOS conducting and the NMOS blocking, the output is pulled toward VDD, producing a HIGH output.
2. On the flip side, when the input is HIGH (VDD), the NMOS transistor is ON because its gate-to-source voltage is above the threshold voltage. The PMOS transistor is OFF because its gate and source are both at VDD, giving a gate-to-source voltage of about 0 V. With the NMOS conducting and the PMOS blocking, the output is pulled toward ground, producing a LOW output.

Next up is the AND gate. Unlike the NOT gate, which only required two MOSFETs, this AND gate uses six: three PMOS and three NMOS.

The AND gate produces a HIGH output only when both inputs are HIGH. If either or both inputs are LOW, the output is LOW.

Circuit Design

A CMOS NAND gate uses two PMOS transistors connected in parallel and two NMOS transistors connected in series. Since NAND produces the inverse of AND, I added a NOT gate at its output to obtain the AND function.

The circuit consists of two stages:

1. The NAND Stage
2. Two BSS84 PMOS transistors connected in parallel form the pull-up network.
3. Two 2N7002 NMOS transistors connected in series form the pull-down network.
4. Each input, A and B, controls one PMOS and one NMOS transistor.
5. The Inverter Stage
6. One BSS84 PMOS transistor and one 2N7002 NMOS transistor form the inverter.
7. Both transistor gates connect to the NAND output.
8. Their drains connect together to form the final AND output.
9. The PMOS source connects to the positive supply, while the NMOS source connects to ground.

Operating Principle

1. When both inputs are LOW: Both PMOS transistors in the NAND stage conduct, while both NMOS transistors are OFF. The pull-up network pulls the NAND output HIGH. The inverter then changes this to a LOW AND output.
2. When only one input is HIGH: The PMOS transistor controlled by the LOW input conducts, keeping a path from the supply to the NAND output. Although one NMOS transistor is ON, the other is OFF. Since the NMOS transistors are connected in series, both must conduct to complete the pull-down path. The NAND output therefore remains HIGH, and the inverter produces a LOW AND output.
3. When both inputs are HIGH: Both NMOS transistors conduct, creating a complete path from the NAND output to ground. Both PMOS transistors are OFF. The NAND output is pulled LOW, and the inverter changes this to a HIGH AND output.

Finally, the OR gate. Like the AND gate, it uses six MOSFETs: three PMOS and three NMOS.

The OR gate produces a HIGH output when either or both inputs are HIGH. The output is LOW only when both inputs are LOW.

Circuit Design

A CMOS NOR gate uses two PMOS transistors connected in series and two NMOS transistors connected in parallel. Since NOR produces the inverse of OR, I added a NOT gate at its output to obtain the OR function.

The circuit consists of two stages:

1. The NOR Stage
2. Two BSS84 PMOS transistors connected in series form the pull-up network.
3. Two 2N7002 NMOS transistors connected in parallel form the pull-down network.
4. Each input, A and B, controls one PMOS and one NMOS transistor.
5. The Inverter Stage
6. One BSS84 PMOS transistor and one 2N7002 NMOS transistor form the inverter.
7. Both transistor gates connect to the NOR output.
8. Their drains connect together to form the final OR output.
9. The PMOS source connects to the positive supply, while the NMOS source connects to ground.

Operating Principle

1. When both inputs are LOW: Both PMOS transistors in the NOR stage are ON, creating a complete path from the supply to the NOR output, while both NMOS transistors are OFF. The NOR output is pulled HIGH, and the inverter changes this to a LOW OR output.
2. When only one input is HIGH: The NMOS transistor controlled by the HIGH input is ON, pulling the NOR output to ground. The PMOS transistor controlled by that same input is OFF, and since the PMOS transistors are in series, this breaks the path to the supply. The NOR output is LOW, and the inverter produces a HIGH OR output.
3. When both inputs are HIGH: Both NMOS transistors are ON, pulling the NOR output to ground, while both PMOS transistors are OFF. The NOR output is LOW, and the inverter changes this to a HIGH OR output.

Before designing the PCBs, I simulated the circuits in LTspice. All circuits were simulated using 5V and a transient duration of 80ms.

NOT Gate Simulation Settings

The NOT gate uses a pulse input with the settings: PULSE(0 5 0 0 0 5m 10m 100).

This allows the voltage source to switch between 5V (HIGH) and 0V (LOW), so it stays at 5V for 5ms and repeats every 10ms.

The expected output was that when A0 is HIGH, the output would be LOW and vice versa.

AND Gate Simulation Settings

The AND gate uses the settings:

1. Initially, PULSE(0 5 0 1u 1u 10m 20m 100) for input A and PULSE(0 5 0 1u 1u 5m 10m 100) for input B.
2. Final, PULSE(0 5 0 1u 1u 10m 20m 100) for input A and PULSE(0 5 0 10u 10u 5m 10m 100) for input B.

OR Gate Simulation Settings

The OR gate uses the settings: PULSE(0 5 0 1u 1u 10m 20m 100) for input A and PULSE(0 5 0 1u 1u 5m 10m 100) for input B.

NB: Input A has a longer time period to account for the 1, 1, 0, 0 input (10m, 20m) and a 1us rise and fall time. Input B has a similar pulse setting to that of the NOT gate, just a slight change in the rise and fall time being 1us for the initial run and 10us for the final run.

Results

1. The NOT gate produced its expected output, where if the input were HIGH, the output would be LOW.
2. The AND gate produced its expected output, where if both inputs are HIGH, the output would be HIGH. Every other input combination gives LOW. For the initial simulation, there are some voltage spikes at 10ms, 30ms, 50ms and 70ms that indicate switching glitches between HIGH and LOW. With equal 1us edges there’s a brief overlap where both inputs read HIGH, which produced the spikes. Slowing B’s rising edge lets A finish falling first. After increasing the rise and fall time to 10us for input B, the spikes were no longer visible.
3. The OR gate produced its expected output, where the output is HIGH whenever at least one input is HIGH, and LOW only when both are LOW.

Now knowing the circuits were functioning as designed, I made the PCBs in KiCad for the first design and EasyEDA for the final design.

I have used KiCad before, but I prefer EasyEDA for its JLCPCB integration. It also makes footprint selections much simpler than KiCad. To make the boards DIP-style, I used a row spacing of 7.62mm between the two rows of pin headers. Pin headers use a pitch of 2.54mm to match the pitch on a typical breadboard. The NOT gate only uses one layer (bottom), while the AND and OR gates use two layers (bottom and top). The data traces use 0.254mm trace width while the power traces (VDD and GND) use 0.5mm to carry more current.

I used JLCPCB for fabrication and got 5 of each board with 1.6mm thickness, black soldermask, and leaded HASL (hot air solder leveling) surface finish for around $3 (shipping included) with a coupon. I soldered the transistors myself using a hot plate and a soldering iron for the pin headers.

Gerber Files

To generate the input signals, I wrote two simple Arduino sketches. In the NOT sketch, pin 11 = A, while in the AND/OR sketch, pin 12 = A and pin 11 = B. I added an LED in series with a 220ohm resistor to the output on the boards to show the output state visually.

Based on the images, it can be said that all three boards performed as designed. There are some minor spikes and fluctuations on the oscilloscope readings which likely indicate that some noise was picked up during the test.

A few notes:

1. If the boards are powered from a separate power supply from the Arduino, ensure all ground connections are tied together so the inputs can be referenced properly
2. It is fairly tedious to keep re-uploading the NOT gate's sketch each time you want to test its output, so for convenience, you can just use pin 11 from the AND/OR sketch. Pin 11 already alternates between HIGH and LOW signals every second, which is all the NOT gate needs.
3. If you don't have an Arduino, you can manually input the signals with a 5V source and a GND connection. So, for HIGH signals, use 5V and for LOW signals, GND.

NB: Do not leave any input pins floating. A CMOS input that’s connected to nothing can pick up noise and give messy outputs, so each input should always be tied firmly to 5V or GND.

Rather than having the LED on the output as a separate component, the LED could be integrated on the board.